1. Field of the Invention
The invention relates to a reference current generating circuit, particularly to a reference current generating circuit capable of compensating a deviation of a standard current from a preset value due to aged deterioration of the circuit.
2. Description of the Background Art
With increasing miniaturization of semiconductor devices in recent years, a phenomenon has come to the fore in which a threshold voltage Vth of a field effect transistor is increased with time due to Hot Carrier Injection (HCI) and Negative Bias Temperature Instability (NBTI). As a result of the increased threshold voltage Vth of the field effect transistor, the current of the field effect transistor is decreased and the characteristics of the semiconductor device are deteriorated. Accordingly, when designing an integrated circuit board in which highly miniaturized field effect transistors are used, it is necessary to consider the deterioration of characteristics of the field effect transistor at the End Of Life (EOL).
A sense circuit for a flash memory determines read data to be “1” when a cell current is larger than a standard current, and determines the read data to be “0” when a cell current is smaller than the standard current. Here, a memory cell is called “on-cell” when “1” is stored in the memory cell, and is called “off-cell” when “0” is stored in the memory cell.
A memory cell array in which such memory cells are arranged in a matrix has on-cell and off-cell currents which are distributed within certain ranges due to variation in characteristics of each memory cell. Consequently, the value of the standard current to be compared with the memory cell current is desirably set in an intermediate range between the lower limit of the on-cell current distribution and the upper limit of the off-cell current distribution.
To achieve such setting, current trimming has been performed for each chip with a conventional reference current generating circuit before shipment of the chips, so that the value of the standard current is set within the intermediate range. After the trimming data has been stored in a register built in a reference current generating circuit, the chip is shipped.
Japanese Patent Application Publication No. 2008-192232, for example, discloses a method of adjusting a reference level of a reference cell used for programming and reading of data to and from a nonvolatile memory cell. The method can thereby reduce shift of a reference level of the reference cell which would occur due to a charge gain, without reducing read-out margin and increasing the chip area.
However, depending on the characteristics of the memory cell, the width of the intermediate range within which the value of the standard current is set may become extremely narrow, e.g. 1 μA or less. The deterioration of the characteristics of elements in a reference current generating circuit at EOL leads to a reduction in value of the standard current. As a result, the value of the standard current at EOL may be within the range of the off-cell current distribution, thereby causing a malfunction in reading out an off-cell.
In the method disclosed by Japanese Patent Application Publication 2008-192232, the reference level of the reference cell is used as a standard current to be compared with a cell current. This leads to a problem that if the widths of the on-cell and the off-cell current distributions are increased, it becomes difficult to adjust the reference level within the intermediate range between the lower limit of the on-cell current distribution and the upper limit of the off-cell current distribution.